# 2024-05-01

## Introduction

> **Summary**

> **keywords**

> **TODO**

> **HW**

> **Exercise**\*

> **Next time**

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## Static Timing Analysis

### Circuit model

* has 'launch model(L)', 'logic model(l)', 'Capture(C)'
* logic is a combinational logic
* L and C are flip-flops.
* Total operations are assumed done in 1 single clock period.

### Setup check

* minimum time.
* $Q$ is available after time $t\_p$
* $t\_{l,max}$ is the max time to go over logic model.
* $t\_{su}$ is the time required for stable signal to reach capture flip-flop.
* $t\_j$ is the clock jitter time.
* $t\_{skew}$ is because of time skew from the logic in clock signal. it is the signal difference between launch model and that of the capture model gets.

### Hold Check

* checking when there is multiple paths.
* we are making sure that on the fastest path, the signal waits enough until the slow one arrives.
* LHS is the longest path, RHS is the shortest path.
* minus jitter is because of the shortest path